;/*****************************************************************************
; * @file:    startup_me32g030.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
; *           for the ME32S003 Device Series GCC compiler only
; * @version: V1.0
; * @date:    2016/06/21
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
; * processor based microcontrollers.  This file can be freely distributed 
; * within development tools that are supporting such ARM based processors. 
; *
; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/


/*****************************************************************************/
/* startup_me32s003.s: Startup file for CMSDK device series               */
/*****************************************************************************/
/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
/*****************************************************************************/

/*
//*** <<< Use Configuration Wizard in Context Menu >>> ***
*/


    .equ    Stack_Size, 0x00000200
    .section ".stack", "w"
    .align  3
    .globl  __cs3_stack_mem
    .globl  __cs3_stack_size
__cs3_stack_mem:
    .if     Stack_Size
    .space  Stack_Size
    .endif
    .size   __cs3_stack_mem,  . - __cs3_stack_mem
    .set    __cs3_stack_size, . - __cs3_stack_mem


    .equ    Heap_Size,  0x00000100

    .section ".heap", "w"
    .align  3
    .globl  __cs3_heap_start
    .globl  __cs3_heap_end
__cs3_heap_start:
    .if     Heap_Size
    .space  Heap_Size
    .endif
__cs3_heap_end:


/* Vector Table */

    .section ".cs3.interrupt_vector"
    .globl  __cs3_interrupt_vector_cortex_m
    .type   __cs3_interrupt_vector_cortex_m, %object

__cs3_interrupt_vector_cortex_m:
    .long   __cs3_stack                 /* Top of Stack                  */
    .long   __cs3_reset_cortex_m        /* Reset Handler                 */
    .long   NMI_Handler                 /* NMI Handler                   */
    .long   HardFault_Handler           /* Hard Fault Handler            */
    .long   0                           /* Reserved                      */
    .long   0                           /* Reserved                      */
    .long   0                           /* Reserved                      */
    .long   0                           /* Reserved                      */
    .long   0                           /* Reserved                      */
    .long   0                           /* Reserved                      */
    .long   0                           /* Reserved                      */
    .long   SVC_Handler                 /* SVCall Handler                */
    .long   0                           /* Reserved                      */
    .long   0                           /* Reserved                      */
    .long   PendSV_Handler              /* PendSV Handler                */
    .long   SysTick_Handler             /* SysTick Handler               */

    /* External Interrupts */
                .long     WDT_IRQHandler          /*  16+ 0: */
                .long     BOD_IRQHandler       /*  16+ 1:  */
                .long     PMWFAULT_IRQHandler             /*  16+ 2: */
                .long     PA_IRQHandler       	/*  16+ 3:  */
                .long     PB_IRQHandler       	/*  16+ 4:       */
                .long     PC_IRQHandler       	/*  16+ 5:       */
                .long     DMA_IRQHandler       	/*  16+ 6:        */
                .long     BTIM0_IRQHandler           /*  16+ 7:              */         
                .long     BTIM1_IRQHandler           /*  16+ 8:              */
                .long     BTIM2_IRQHandler             /*  16+ 9:    */
                .long     BTIM3_IRQHandler             /*  16+10:     */     
                .long     CTIM0_IRQHandler             /*  16+11:    */
                .long     CTIM1_IRQHandler           	/*  16+12:       */
                .long     ADC_IRQHandler           	/*  16+13:        */
                .long     I2C0_IRQHandler           	/*  16+14:         */
                .long     I2C1_IRQHandler             /*  16+15:         */
                .long     SPI0_IRQHandler             /*  16+16:            */
                .long     SPI1_IRQHandler             /*  16+17:    */
                .long     PWM_IRQHandler             /*  16+18:          */
                .long     UART0_IRQHandler           	/*  16+19:          */
                .long     UART1_IRQHandler        					/*  16+20:       */
                .long     UART2_IRQHandler           				/*  16+21:     */
                .long     UART3_IRQHandler            /*  16+22:             */
                .long     ACMP0_IRQHandler            /*  16+23:            */
                .long     ACMP1_IRQHandler                          /*  16+24:         */
                .long     0                          /*  16+25: Reserved              */
                .long     0                          /*  16+26: Reserved              */
                .long     0                          /*  16+27: Reserved              */
                .long     0                          /*  16+28: Reserved              */
                .long     0                          /*  16+29: Reserved              */
                .long     0                          /*  16+30: Reserved              */
                .long     0                          /*  16+31: Reserved              */

    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m

    .thumb

/* Reset Handler */

    .section .cs3.reset,"x",%progbits
    .thumb_func
    .globl  __cs3_reset_cortex_m
    .type   __cs3_reset_cortex_m, %function
__cs3_reset_cortex_m:
    .fnstart
   /* LDR     R0, =SystemInit */
   /* LDR     R0, =main */
   /* BLX     R0 */

    MOVS    R0,#0 /* Clear the registers to avoid unknown value in verilog simulations */
    MOV     R1,R0
    MOV     R2,R0
    MOV     R3,R0
    MOV     R4,R0
    MOV     R5,R0
    MOV     R6,R0
    MOV     R7,R0
    MOV     R8,R0
    MOV     R9,R0
    MOV     R10,R0
    MOV     R11,R0
    MOV     R12,R0

    LDR     R0,=_start
    BX      R0
    .pool
    .cantunwind
    .fnend
    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m

    .section ".text"

/* Exception Handlers */

    .weak   NMI_Handler
    .type   NMI_Handler, %function
NMI_Handler:
    B       .
    .size   NMI_Handler, . - NMI_Handler

    .weak   HardFault_Handler
    .type   HardFault_Handler, %function
HardFault_Handler:
    B       .
    .size   HardFault_Handler, . - HardFault_Handler

    .weak   SVC_Handler
    .type   SVC_Handler, %function
SVC_Handler:
    B       .
    .size   SVC_Handler, . - SVC_Handler

    .weak   PendSV_Handler
    .type   PendSV_Handler, %function
PendSV_Handler:
    B       .
    .size   PendSV_Handler, . - PendSV_Handler

    .weak   SysTick_Handler
    .type   SysTick_Handler, %function
SysTick_Handler:
    B       .
    .size   SysTick_Handler, . - SysTick_Handler


/* IRQ Handlers */

    .globl  Default_Handler
    .type   Default_Handler, %function
Default_Handler:
    B       .
    .size   Default_Handler, . - Default_Handler

/* Macro to map "weak" peripheral interrupt to default handler */
    .macro  IRQ handler
    .weak   \handler
    .set    \handler, Default_Handler
    .endm


                IRQ     WDT_IRQHandler          /*  16+ 0: */
                IRQ     BOD_IRQHandler       /*  16+ 1:  */
                IRQ     PMWFAULT_IRQHandler             /*  16+ 2: */
                IRQ     PA_IRQHandler       	/*  16+ 3:  */
                IRQ     PB_IRQHandler       	/*  16+ 4:       */
                IRQ     PC_IRQHandler       	/*  16+ 5:       */
                IRQ     DMA_IRQHandler       	/*  16+ 6:        */
                IRQ     BTIM0_IRQHandler           /*  16+ 7:              */         
                IRQ     BTIM1_IRQHandler           /*  16+ 8:              */
                IRQ     BTIM2_IRQHandler             /*  16+ 9:    */
                IRQ     BTIM3_IRQHandler             /*  16+10:     */     
                IRQ     CTIM0_IRQHandler             /*  16+11:    */
                IRQ     CTIM1_IRQHandler           	/*  16+12:       */
                IRQ     ADC_IRQHandler           	/*  16+13:        */
                IRQ     I2C0_IRQHandler           	/*  16+14:         */
                IRQ     I2C1_IRQHandler             /*  16+15:         */
                IRQ     SPI0_IRQHandler             /*  16+16:            */
                IRQ     SPI1_IRQHandler             /*  16+17:    */
                IRQ     PWM_IRQHandler             /*  16+18:          */
                IRQ     UART0_IRQHandler           	/*  16+19:          */
                IRQ     UART1_IRQHandler        					/*  16+20:       */
                IRQ     UART2_IRQHandler           				/*  16+21:     */
                IRQ     UART3_IRQHandler            /*  16+22:             */
                IRQ     ACMP0_IRQHandler            /*  16+23:            */
                IRQ     ACMP1_IRQHandler                          /*  16+24:         */
	
    .end


